Fpga Implementations of Neural Networks
Fpga Implementations of Neural Networks Springer-Verlag GmbH, "The development of neural networks has now reached the stage where they are employed in a large variety of practical contexts. However, to date the majority of such implementations have been in software. While it is generally recognised that hardware implementations could, through performance advantages, greatly increase the use of neural networks, to date the relatively high cost of developing Application-Specific Integrated Circuits (ASICs) has meant that only a small number of hardware neurocomputers has gone beyond the research-prototype stage. The situation has now changed dramatically: with the appearance of large, dense, highly parallel FPGA circuits it has now become possible to envisage putting large-scale neural networks in hardware, to get high performance at low costs. This in turn makes it practical to develop hardware neural-computing devices for a wide range of applications, ranging from embedded devices in high-volume/low-cost consumer electronics to large-scale stand-alone neurocomputers. Not surprisingly, therefore, research in the area has recently rapidly increased, and even sharper growth can be expected in the next decade or so. Nevertheless, the many opportunities offered by FPGAs also come with many challenges, since most of the existing body of knowledge is based on ASICs (which are not as constrained as FPGAs). These challenges range from the choice of data representation, to the implementation of specialized functions, through to the realization of massively parallel neural networks; and accompanying these are important secondary issues, such as development tools and technology transfer. All these issues are currently being investigated by a large number of researchers, who start from different bases and proceed by different methods, in such a way that there is no systematic core knowledge to start from, evaluate alternatives, validate claims, and so forth. FPGA Implementations of Neural Networks aims to be a timely one that fill this gap in three ways: First, it will contain appropriate foundational material and therefore be appropriate for advanced students or researchers new to the field. Second, it will capture the state of the art, in both depth and breadth and therefore be useful researchers currently active in the field. Third, it will cover directions for future research, i. e. embryonic areas as well as more speculative ones. TOC:Preface. - FPGA Neurocomputers; A. R. Omondi, J. C. Rajapakse and M. Bajger. - Arithmetic precision for BP networks; M. Moussa, S. Areibi and K. Nichols. - FPNA: Concepts and properties; B. Girau. - FPNA: Applications and implementations; B. Girau. - Back-Propagation Algorithms Achieving 5 GOPS on the VirtexE; K. Paul and S. Rajopadhye. - FPGA Implementation of Very Large Associative Memories; D. Hammerstrom, C. Gao, S. Zhu and M. Butts. - FPGA Implementations of Neocognitrons; A. Noriaki Ide and J. Hiroki Saito. - Self Organizing Feature Map for Color Quantization on FPGA; C-H. Chang, M. Shibu and R. Xiao. - Implemention of Self-Organizing Feature Maps in Reconfigurable Hardware; M. Porrmann, U. Witkowski and U. Rückert. - FPGA Implementation of a Fully and Partially Connected MLP; A. Canas, E. M. Ortigosa, E. Ros and P. M. Ortigosa. - FPGA Implementation of Non-Linear Predictors; R. Gadea-Girones and A. Ramrez-Agundis. -The REMAP Reconfigurable Architecture: a retrospective; L. Bengtsson, A. Linde, T. Nordstrom, B. Svensson and M. Taveniku. ", , ,

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